1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method therefor.
2. Description of Related Art
As a nonvolatile semiconductor memory device in that a storage content is not erased even if power is turned off, a split gate type nonvolatile semiconductor memory device is known, as described in U.S. Pat. No. 6,525,371 B2. FIG. 1 is a cross-sectional view illustrating a configuration of the split gate type nonvolatile semiconductor memory device described in the above U.S. Pat. No. 6,525,371 B2. In this split gate type nonvolatile semiconductor memory device, a plurality of memory elements (hereinafter to be referred to as split gate type nonvolatile semiconductor memory cells 101) are formed.
As illustrated in FIG. 1, the split gate type nonvolatile semiconductor memory cell 101 is provided with a first source/drain diffusion layer 103 and second source/drain diffusion layers 104 which are formed on a substrate 102. Also, the nonvolatile semiconductor memory cell 101 is provided with floating gates 105 and control gates 106. The floating gate 105 is formed on the substrate 102 through a gate oxide film 107. Also, the control gate 106 is formed on the substrate 102 through a tunnel oxide film 108. Further, the tunnel oxide film 108 extends between the floating gate 105 and the control gate 106. A polysilicon plug 109 is formed on the first source/drain diffusion layer 103. The floating gate 105 is formed to have an acute angle portion. Also, a spacer 111 is formed on the floating gate 105.
An operation of the split gate type nonvolatile semiconductor memory cell 101 in U.S. Pat. No. 6,525,371 B2 will be described. FIGS. 2A to 2C are diagrams showing operations of a conventional split gate type nonvolatile semiconductor memory cell 101. Of the split gate type nonvolatile semiconductor memory cell 101, a write operation is shown in FIG. 2A, an erase operation in FIG. 2B, and a read operation in FIG. 2C.
As shown in FIG. 2A, when data is written in the split gate type nonvolatile semiconductor memory cell 101, the first source/drain diffusion layer 103 functions as a drain, and a relating one of the second source/drain diffusion layers 104 functions as a source. Upon the data write, the first source/drain diffusion layer 103 of the memory cell 101 is set to a higher voltage than the relating second source/drain diffusion layers 104. Thus, hot electrons (electrons in a high energy state) are generated on the source side of a channel, and are injected into the floating gate 105 through the gate oxide film 107. Such an operation is referred to as source side hot electron injection. Thus, the data is written. After the data is written, the floating gate is brought into a negatively charged state.
As shown in FIG. 2B, when data is erased from the memory cell 101, electrons are drawn out into the control gate 106 through the tunnel oxide film 108 by an FN tunneling current from the floating gate 105. Thus, the data is erased. That is, upon the erasure, the electrons are adapted to be drawn out from the floating gate 105 by applying a voltage to the control gate 106 to concentrate electric filed on a sharp tip portion (acute angle portion) of the floating gate 105. After the erasure, the floating gate is brought to a positively charged state.
As shown in FIG. 2C, when data is read from the memory cell 101, a predetermined voltage is applied to the control gate 106 to activate a transistor of the control gate 106, the first source/drain diffusion layer 103 as a source and the relating second source/drain diffusion layer 104 as a drain. At this time, current flowing between the source and the drain is varied based on the charges held in the floating gate 105. Thus, the data is read out.
As an information processing technique has been advanced, miniaturization of the split gate type nonvolatile semiconductor memory cell 101 is required.
When data is written in the split gate type nonvolatile semiconductor memory cell 101, a voltage of the floating gate 105 is increased through the functions of a capacitor formed between the first source/drain diffusion layer 103 and the floating gate 105. Accordingly, the floating gate 105 should be overlapped with the first source/drain diffusion layer 103 as seen from the above. If a size of the floating gate 105 is reduced along with the miniaturization of the memory cell 101, an overlap region between the first source/drain diffusion layer 103 and the floating gate 105 is also reduced. The reduction of the overlap region may cause a problem in the data write. A technique capable of appropriately writing data while reducing the size of the floating gate 105 is known in Japanese Patent Application Publication (JP-P2004-289161A).
FIG. 3 is a cross-sectional view illustrating a configuration of a floating gate type memory cell array described in Japanese Patent Application Publication (JP-P2004-289161A). In the memory cell array, each memory cell includes a trench formed in a surface region of a semiconductor substrate 210. A memory cell is provided with a source region 258 formed under the trench. A polysilicon block 260 is connected to the source region 258. Further, the memory cell is provided with a drain region 280 formed along a surface of the substrate 210. A channel region 204 is provided between the source and drain regions 258 and 280. The channel region 204 includes a first portion 204a vertically extending along a sidewall of the trench, a second portion 204b horizontally extending along the surface of the substrate, and a third portion 204c extending from the first portion 204a to the source region 258.
A floating gate 246a of the memory cell is arranged in a trench to be adjacent to and insulated from the first portion 204a of the channel region 204. A control gate 268 is arranged on the second portion 204b of the channel region 204 to be insulated from the second portion 204b. A sidewall of the trench intersects with the substrate surface at an acute angle, and thereby a sharp edge is formed. The second portion 204b of the channel region 204 extends toward the sharp edge and the floating gate from the second portion 204b to define a path for programming the floating gate through hot electron injection.
The floating gate type memory cell described in Japanese Patent Application Publication (JP-P2004-289161A) is provided with the floating gate 246a formed in the trench, and the polysilicon block 260 buried inside the substrate 210. Also, the floating gate 246a and the poly block 260 are both buried in the substrate, and an area of a portion opposing to each other is increased. Thus, the floating gate 246a is set to a higher voltage than a voltage of the source region 258 based on capacitive coupling between the polysilicon block 260 and the floating gate 246a. 
As described above, in the floating gate type memory cell, a first capacitor is formed by the floating gate 246a and an overlapping portion of it with the source region 258. Also, a second capacitor is formed by the floating gate 246a and an overlapping portion of it with the polysilicon block 260. The floating gate type memory cell increases a voltage of the floating gate 246a through functions of the first and second capacitors.
Also, the trench is formed in the substrate 210 to form the second capacitor. The polysilicon block 260 is formed to extend in a depth direction of the trench. Also, the floating gate 246 is formed to extend in a depth direction of the trench.
The trench depths and widths of all of the memory cells are adaptive to respectively have the same values to increase a voltage of the floating gate 246a through the function of the second capacitor 2 to appropriately operate the floating gate type memory cell.
Also, the channel region of the floating gate type memory cell is formed by implanting impurities into the substrate. The impurities to be implanted into the substrate are required to be uniformly implanted into the substrate. As described above, the channel region of a conventional floating gate type memory cell is formed in the depth direction along a sidewall of the trench. For all of the memory cells, it is extremely difficult to uniformly implant the impurities in the depth direction.